Xilinx Design Summary

QBTRIG_2007-11-26 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	87	9,312	1%
Number of 4 input LUTs	69	9,312	1%
Logic Distribution
Number of occupied Slices	56	4,656	1%
Number of Slices containing only related logic	56	56	100%
Number of Slices containing unrelated logic	0	56	0%
Total Number of 4 input LUTs	110	9,312	1%
Number used as logic	69
Number used as a route-thru	41
Number of bonded IOBs	13	232	5%
IOB Flip Flops	6
IOB Master Pads	2
IOB Slave Pads	2
Number of GCLKs	2	24	8%
Number of DCMs	1	4	25%
Total equivalent gate count for design	8,410
Additional JTAG gate count for IOBs	624

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met