How to load new firmware
1. Power up Spartan 3E Starter Kit board
2. Attach USB JTAG cable (must be done after power-up or computer gets confused)
Start the program 'Xilinx ISE 9.2i' by
double-clicking the icon on the desktop or by accessing it through the
Start menu. By default, it loads the last project (which is
probably QBtrig_2007-11-26, but if not, you can open the correct
project when it finishes loading the default).
The QB MCLK trigger project is located on the Windows machine at:
C:/JLR/QBtrigger-clock/QBtrig_2007-11-26/QBtrig_2007-11-26.ise
Note: This machine is very slow. Be patient!
How to load a .bit file onto the FPGA
Do this to test functionality of the new firmware before
programming the flash memory to load the firmware onto the FPGA
automatically.
1. In the middle-left frame of the ISE window,
make sure that "Synthesize" and "Implement Design" each have
the 
icon (there are a few warnings, but no errors during these steps), and that "Generate Programming File" has a 
.
If not, double-click the steps that don't. Eventually (since the
computer is old and slow) the program will execute the necessary
actions to synthesize and implement the design. When all the
correct icons are displayed, click the '+' next to "Generate
Programming File" to expand its menu.
2. Double-click "Configure Device (iMPACT)" at
the bottom of the "Generate Programming File" menu. After about 20-30
seconds, a separate window will pop up. Choose "Configure devices using
Boundary-Scan (JTAG)" with the option "Automatically connect to a cable
and identify Boundary-Scan chain." Then click "Finish."
3. A chain of 3 Xilinx chips will show up in
the top-right ISE window. The first (xc3s500e) is the Spartan 3E FPGA,
the second (xcf04s) is the Xilinx Flash PROM, and the third (xc2c64a)
is the Xilinx Coolrunner CPLD. A separate window will pop up
asking you to choose a configuration file for each of these devices.
Choose "counter.bit" for the FPGA, then click "Bypass" for the other 2
devices.
4. In the middle-left window, click once on
"Available Operations are:" to
get the program to understand that you want to do something other than
assign a new configuration file (REALLY, click on that text, not
on one of
the tempting green arrows). Then in the top-right ISE window,
right-click on the FPGA (xc3s500e) and choose "Program," then click
"OK." A blue box will pop up to tell you that the programming
has finished successfully. Then check that the firmware behaves
as you hope by checking the outputs with the scope.
How to load an .mcs file onto the PROM
After verifying that the firmware behaves as it should, you can
program the flash memory to load the FPGA automatically upon power-up.
1. In the top-left frame of the ISE window,
double-click "PROM File Formatter." In the window that pops up,
choose the options "Xilinx PROM" and "MCS," then change the PROM
File Name to "counter" and click "Next."
2. In the drop-down menu for "Select a PROM
(bits):" choose "xcf04s" and click "Add." Then click "Next" followed by
"Finish." Click "OK" in the window that pops up with the text
"Start adding device file to Data Stream: 0." Choose
"counter.bit" and click "Open." Choose "No" in the window that
says "Would you like to add another device file to Data Stream: 0."
Then click "OK" to complete. Now double-click "Generate File..."
in the middle-left ISE window. A blue box will display "PROM File
Generation Succeeded" if you did everything correctly.
3. In the top-left ISE window, double-click
"Boundary Scan." Right-click on the middle device 'xcf04s' and choose
"Assign new configuration file." Then select "counter.mcs" and click
"Open." After clicking on the middle-left frame "Available
operations are:" once, right-click xcf04s again and choose
"Program." In the window that pops up, choose "Verify" and "Erase
Before Programming" and "Load FPGA." Then click "OK." A blue box will
pop up with "Program Succeeded" if it did...
You're finished! Cycle power and check that yellow "DONE" LED comes on.