This note is an update report on progress on the fast waveform
digitizer; I will cover both the pcb board itself and related system
activities. I will take as a starting point the March collaboration
meeting.
At that time, we had just selected a designer to do the pcb layout. The
design was delivered around April 20th and sent for fabrication shortly
thereafter. Unfortunately, there were some administrative delays with
the P/O and the two-week turn on the board did not start until May 5. We
got 5 boards delivered on May 21 and I then assembled one channel and
debugging began May 24.
The first big surprise was that a design error connected -5.2 V to
ground at a via that was missing its isolation on the ground plane.
This has been fixed on all the prototype boards by drilling out that via
and reconnecting the appropriate trace with a wire. The next couple of
weeks were spent identifying other errors, mostly in part value. The
most troublesome was a PAL that was inadvertently burned with the wrong
source code. This single-channel board was working properly by about
June 11.
In parallel with this, there was a lot more going on. I was identifying
vendors for assembly and trying to solve the problem of how to form and
trim the leads on the ASIC. This is quiet a story (I'll spare you) and
it consumed a disproportionate amount of my energy. The ASIC is
delivered with the leads sticking straight out of the package; to
assemble it on a pcb one must form them into some leg shape and also
trim them. Because they are very fragile (.025" pitch), this is very
hard to do neatly by hand, as I did for the prototype board. Anyway,
through the Surface Mount Network Help-line 1-800-762-8937, I finally
got in contact with a division of Texas Instruments in Dallas who take
outside work and just recently completed a job with the necessary die.
They offered to build a free prototype board and I took delivery of a
full four channel board around June 30. I have sent them the remaining
three pcb's for assembly. I will bring these to Italy for system tests
in August.
More parallel work went on with the amplifier daughtercard. The first
version, which I showed you at the March meeting, did not have
acceptable isolation between the analog section (amplifier) and digital
section (discriminators). Bill Earle determined a number of revisions
and a new layout was done and we have been working with a revised
version of the card since early May. These circuits remain very
technically challenging. For example, we need to discriminate at levels
around 3 mV while a) not disturbing the output pulse and b) handling
large input signals up to -10 V. All this must happen with the
discriminator bits timed to line up with the FADC samples. John Hong
has been getting involved in this part of the project and worked with
Bill to track down and eliminate some sources of poor pulse shape that
showed up in the layed out board (with trace capacitance) but didn't
show up in the 3-D wired prototypes. At any rate, we think this is under
control and we have a handful of tweaked daughtercards to go with the
motherboards. The next iteration should be designed and fabricated over
the next several weeks.
Bob Webb and Ann David have designed and built the power backplane (J3)
and a power supply enclosure. We received one a couple months ago and
Bill Worstell carried back from Italy our test VME crate. John assembled
and tested these and we are now working in a functional example of the
crate/power to be used in Italy. There were a couple of minor hitches: 1)
the VME crate also needs +-12V for other VME cards (not the WFD), the
TAMU people are seeing to that now and 2) in-crate computers (not the
VIC boards however) need access to the J2 connector in the back, where
the power enclosure hinders access. I'm still thinking about the best
way to handle this. In any event, the 6 system crates should be shipped
from TAMU to Gran Sasso soon. I hear that cable making is also imminent.
Speaking of the VIC interface, we have requested that Giorgio Giacomelli
purchase these to repay some money owed to the MACRO/USA group. We have
not yet heard if the order has been placed. The DAQ group (Ronga et al)
has been installing and testing their end of the system recently.
Younan Lu has spent some time working with them and has learned about
how the system will work. We have two strategies for interfacing with
this system. The one that I believe will be implemented first is to
modify the VME readout software to read the wfd information in an
intelligent way that uses the timeword information to only record the
inormation for a specified time window. I have written routines for my
test DAQ and the overhead of the extra calculations is not large (25%)
and the transfer rate is still quite high (> 4 Mb/sec). The next step
(due for my trip in August) is to translate them from C to EPASCAL for
VAXELN. The second strategy is to have in-crate computers do this
processing and provide the daq with structured data, but I feel that
this will require considerable development time to learn how to pass the
required control information back and forth.
We have heard from Rongzhi about the Stop Manager, which will record and
prioritize the trigger information and provide an appropriately delayed
common stop signal for each SM. Bill Earle is designing a fanout card
for this signal and the common start signal. The electronics design is
rather simple, but the mechanical design is more interesting. This will
be a thin front-panel board that mounts below the WFD crate so that the
signals can be brought up to the cards with short lemo cables in a neat
fashion. This is also the board that will provide the external 200 MHz
clock to each card.
I am pleased to report that our co-users, the muon g-2 experiment, have
been working with the card too. They have taken the 1-channel board
(which now has two channels) to a testbeam at Brookhaven, and seem to be
having good success with it.
So, I'm sure you now want to ask: "When will it be ready?". Fine, but
don't forget to ask: "Will it be reliable? Can we stay in the budget?".
We are doing our best to make sure the last two are answered "Yes".
Given that, here is my current outlook. We have found no show-stopping
problems with the design so far, although Bill and I are still trying to
track down some intermittent bad behavior. I'll bring three boards to
Italy on July 30 and test them there a) with the real ground/noise
environment and b) the real DAQ. By the end of my trip (Aug 23) I hope
to leave behind two or three working boards that can be brought up with
the rest of the recabled and reconfigured electronics. That should
provide a good opportunity to solve most of the system integration
issues. In the meantime, we should have reached sufficient confidence to
start the final version of the board. The few design changes we know of
have already been reported to the layout artist, so that should have
negligible lead-time. The pcb fabrication is typically four weeks. So
is parts procurement, which can go in parallel. But I have recently been
hearing about industry wide shortages of inventory, so I am more worried
on this count and will assume 7 weeks. The assembly lead time for the
first board is relatively short once they have all the parts. The full
production could be done in three weeks. Note: although I am referring
above to the wfd motherboard; the daughterboards should be able to
proceed roughly in parallel. I don't know how long testing will take,
but I will get a better idea when I get the next three boards delivered.
So, my best current estimate:
Week 1: Start production. Get P/O's, start ordering parts.
Week 2: PCB Fabrication lead time (production prototype). Parts lead time.
Week 3: PCB Fabrication lead time (production prototype). Parts lead time.
Week 4: Assemble and Test Production Prototype. Parts lead time.
Week 5: PCB Fabrication lead time (125 boards). Parts lead time.
Week 6: PCB Fabrication lead time (125 boards). Parts lead time.
Week 7: PCB Fabrication lead time (125 boards). Parts lead time.
Week 8: PCB Fabrication lead time (125 boards). Parts lead time.
Week 9: Deliver parts and board: assembly begins.
Week 10: Assembly continues. Test first batch of boards.
Week 11: Assembly continues. Testing continues.
Week 12: Assembly is finished. Testing continues.
So when is Week 1? It is hard to estimate because we have not identified
and solved all of the problems. But my guess is that they will be
identified and solved between now and mid-August, so with that optimism,
I would hope for early in September.
Comments and suggestions are welcome. -Ed