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This is just a brief update, I summarized things more fully last week.
Here at BU, we (Earle, Kearns, Orth) have been reviewing the frontend
card in light of what I learned in August. The three issues to check:
1) glitch on the leading edge of fast signals,
2) crosstalk that sets off discriminator bits and
3) a new steeper response curve.
After probing around the board looking at the crosstalk problem, it
occurred to me that the leading edge glitch may actually be aggravated
by the crosstalk. We put a large signal into one input and look at
the output of the other amplifiers in the same package; we see a
glitch on the other outputs in time with the rising and falling edge.
This glitch goes off to the threshold comparators and can turn on a
discriminator bit; however it also gets summed into the amplifier signal.
It is hard to tell how much of a contribution it makes, and how much
is due to the natural overshoot of the amplifier.
The source of the crosstalk is likely a combination of crosstalk
internal to the amplifier chip and capacitive coupling of some circuit
board traces. We identified several troublespots in the layout that
would be easy to fix. The crosstalk in the chip is not likely to go
away, unless we somehow limited the size of the input signal.
Well, I decided to do the following: take the signal for the threshold
*after* the first diode instead of before, which naturally limits
the signal to the threshold circuit nicely, but causes the DAC values
to effectively be non-linear. This is actually a feature. It is still
linear for low signals, where we will operate, but now we can set a much
higher effective threshold when we turn an input off. It means that
the large input signal never has to go very far on the board. And I can
eliminate one amplifier.
In the meantime, I had Chris testing the new steeper response curve.
It turns out that to achieve that, a particular voltage has to
go from positive to negative, which I couldn't do with a component
change. Chris kludged it in for a test, and verified that it works
as well as the previous curve. We will win incrementally by decreasing
d(Vout)/d(Vin).
Anyway, these fixes seemed too worthwhile to pass up, so I layed out
a new daughtercard. I tried very hard to get the design done by Friday,
which would have allowed me time for a quick jaunt to LNGS while the
boards are being fabricated. Unfortunately, I didn't quite make it-
the design is now done and we will send it out on Monday.
So, I am very hopeful for this latest iteration. We probably could
have lived with the quirks in the last design, so as long as nothing
new and bad was introduced, this should be final. Depending on the
quotations, I may even order the full set now. The new card could be
in as quickly as 10 days (if I can get the saturnine BU bureacracy to
generate a P.O. in a timely fashion). I'll immediately build and test
one here; then send it with John Hong to LNGS and if it looks good
there commence production.
In the meantime, the setup at LNGS is perfectly good for further system
tests. I hope we can get more exercise out of it with the new workers
this month (Chris Walter arrives next week and Younan sometime
thereafter). I got some very good feedback from Francesco regarding
the buffer size problems. I'll put together a text file and leave it
in [MACROUSA.WFDINFO] for your perusal.
With the collaboration meeting coming up, we can again consider a
pre-meeting. I would like to propose the following: if you have any
general wfd stuff to present, put it in the main meeting. I would
still like to have a meeting, but restrict it to online issues.
It doesn't have to be long, but I'd like it to be focused. For example,
we should get the tape making people involved and come up for a strategy
that. Another topic is rate limiting safety measures. The most important
topic is to hash out possible architectures for the readout; decide how
we can test them and schedule those tests. Please think about these
issues, and others I may have left off.
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