ETK 20-JUN-94

This note describes the functionality of the WFD (rev. D) control register.
The 8-bit wide control register is offset from the base address of each 
channel by 0xFFE0. This address is also used to store ASIC generated wfd 
cycles, but a write operation from the VME bus is intercepted and treated 
specially. See the note regarding the Read_Write function for more detail.

There is no way to read-back the current setting of the control register.
Appropriate settings must be maintained through software control.

The 8-bit register uses byte-0 of this address, which is unambiguous if an 
8-bit transfer is performed. If a 16-bit transfer or 32-bit transfer is 
performed, it is the left-most byte in a hexadecimal representation. For 
example, to turn bit 2 on, the data would be 0x04 for 8-bit transfer, 0x0400 
for 16-bit transfer and 0x04000000 for 32-bit transfer. It is also safe to 
simply write 0x04040404 if you cannot remember this.

   Bit Assignments of the Control Register:
   ----------------------------------------------
   Bit 0        Zero Suppression Enable
   Bit 1        Interrupt Enable
   Bit 2        Read_Write Mode Enable
   Bit 3        Stop Address Readback Enable
   Bit 4        Rollover Word Enable
   Bit 5        VME Reset function
   Bit 6        unused
   Bit 7        Threshold DAC clock
   ----------------------------------------------

Notes: 

0) Setting this bit turns zero suppression on.

1) Setting this bit enables interrupts. The interrupt is generated
   when the wfd board is stopped. This function is not implemented
   very well and requires some special instructions to use it. For
   the purposes of MACRO, interrupts are not useful and this should
   not be used.

2) Setting this bit enables VME write access to the wfd memory.
   Because the control register location itself is within the wfd
   channel memory space, further control register operations are
   not possible while in this mode. To exit from this mode, one
   needs to read from the last byte in channel memory (0xFFFF with
   an 8-bit transfer, 0xFFFC with a 32-bit transfer).

3) Setting this bit enables stop address readback. In this mode,
   any read operation on the given channel will result in special
   data being returned, which contains the address offset of the
   last cycle stored when the NIM STOP signal occurred (pointing
   to the ADC data bank). With a 32-bit read, the address offset 
   is contained in bytes 0 and 1.

4) Setting this bit turns on rollover words. A rollover word is
   forced when the 16-bit clock reaches full scale (0xFFFF). If
   a digitization is in progress at this time, the rollover word
   may be 0xFFFE, 0xFFFD or 0xFFFC.
   
5) Setting this bit resets the ASIC. This puts the memory pointer at 
   the end of RAM (0x7FFC for ADC data and 0xFFFC for time/discriminator
   data. When the board is restarted, the data will fill memory beginning
   from this point. It is a momentary signal so this bit need not be zeroed
   after use. This function is not generally useful for MACRO running.

6) Unused. Nominally, this is identified as a VME START function,
   but it does not work as intended.

7) This bit is used as a slow clock to load data into the threshold
   DAC. The threshold data is loaded into the appropriate register
   (0xFFF0 through 0xFFFC) and bit-7 is toggled on and off to clock
   the data into the DAC.