Super-K Outer Detector TDC Front-End
This page collects together information pertaining to the
TDC Front End module planned for the Outer Detector. The
conceptual design has evolved quite a bit over the past
months- to see what has been discussed previously, refer to the
DAQ page at
UW (look under technical information). Also,
Eric Hazen
has a page
with many useful pieces of information regardingthis project.
The main sticking point has been how to implement some sort
of charge measurement. A charge measurement is useful certainly for finding
the entry point of a muon as a seed for inner detector tracking... and
perhaps we can do other things with it. (
see discussion)
Because of WLS jitter, reflected light and late pulses, a simple TOT
is not going to provide a good estimate of Q (see several talks in the Irvine
meeting slides). Some sort of integration is called for, and we are proposing a
gated ADC integration using a QTC chip to multiplex the timing edges
in with the TDC data (for the original sketch of this see Bob S.
talk in the Irvine slides).
Here are our current
specifications for a module.
The heart of the design is the MQT200 chip by
LeCroy. This is the
same chip used in the 1881 ADC that we have considered. We will
post more information about the chip here... until then refer to the
1985 LeCroy manual for a data sheet.
New:
Update email 20-NOV-1995
Here are a few more plots showing progress
with getting this module designed. These are scope measurements from
the single channel daughtercard that was delivered in early June.
This daughtercard is fully functional and can be used in the final
module (motherboard design is in progress). There is not much new
with respect to the MQT200 (although we will soon repeat the ADC/TDC
tests described below). The new work is getting the t/q pulse out
as described in the specifications in a compact design (ESH). The
heart of this is a RS Flip-Flop and PAL to generate the
gate ). The PAL serves double duty in recombining the initial
discriminated t-pulse with the
MQT200 TIME output).
Here is a
figure) illustrating the TQ pulse responding to 3 different
input pulses. The top two traces have about 4x the input charge
as the bottom; it is a little hard to make out the ~8 ns increase
in delta-t in the Q-pulse due to the large pedestal (we will be
looking into minimizing that).
Lab tests (by Mika, Olof): we have compared the QTC output of the
LeCroy MQT200 with a LeCroy 2249 CAMAC ADC. A pmt-like pulse from a
programmable pulser is fed into the 2249 and to the QTC test board for
the MQT200. The ECL output of the QTC test board is sent to a LeCroy
2277 CAMAC TDC (16 bits, 1 ns least count). 300 pulses are measured at
each pulser setting.
Figure 1
shows the response of the QTC to the charge of
the input pulser (using the CAMAC ADC as calibration reference).
Figure 2 shows this response at lower light levels
(30 pulses per setting).
Here is a postscript file of the
schematic .
Here is a
block diagram , and here is a
timing diagram .
The prototype boards are due approximately June 1, and the parts
list should be filled by then as well. Design of the motherboard
will proceed in parallel with testing of this daughtercard.
ETK