4/28/1995
		Super-K Outer Detector ADC/TDC/Hitsum Module
			_Proposed Specifications_
			   E. Hazen, E. Kearns
    

General

    This module provides a self-triggered, gated, linear charge-to-time
    converter (QTC) for measuring the _charge_ of a PMT pulse, as well as
    leading edge timing for the _time_ of the PMT pulse. There is a
    a single ECL output for each PMT, with a short TOT width pulse
    that represents the PMT hit time, followed by a longer variable width
    pulse that is proportional to the PMT charge integrated over the gate
    period. The module will also provide an analog HITSUM output whose
    amplitude is proportional to the number of PMT's over threshold during
    a coincidence window. In addition, a single NIM logic output will be
    provided when the HITSUM for this module is above a separate adjustable
    threshold.

Inputs

    48 PMT signals from HV decoupling card in the form of:
       4x 12-signal ribbon cables, each 50 conductor 0.1" standard header 
       connectors (pinout TBD)
    Optional External Gate and/or Gate Control
       an external gate may be provided, and/or a control signal that
       forces the internal self-triggered gate to fire. To be decided.

Outputs

    48 differential ECL time/charge signals
	on 3x 34-conductor 0.1" standard header connectors 
	    (LeCroy ECLine pinout)
	first pulse is time mark
	second pulse encodes charge
    analog HITSUM output
	linear sum of fixed-width discriminator signals
    NIM TRIG output
	logic output when HITSUM is above adjustable threshold

Adjustable Controls (all are common to 48 channels)
(over a limited range)

    PMT threshold (nominal = 12.5 mV = 1/4 pE)
    TRIG threshold 
    QTC gate width (nominal = 200 ns)
    HITSUM coincidence window (nomina = 200 ns; may be identical to QTC gate)
    NTOT enable recording of multiple TOT edges during gate interval

Packaging

    16 channel PCB, three identical PCB per double width NIM module
    (layout constraints may force other packaging)

Electrical Specs

    Input impedance	    50 or 100 ohms
    Input range [*]	    0-200mA
    
    QTC output range [*]    100-1100ns
    QTC gain [*]	    1ns/10pC

    Differential linearity  10% (or better)
    Integral linearity	    1% (or better)

    [*] - may be changed over a fairly wide range, but cannot be
	  adjusted once a module is built

Timing Sequence

    When the input PMT signal crosses threshold a fixed width timing
    pulse is generated whose width follows the TOT of the PMT
    pulse. This immediately triggers the QTC gate of length 200 ns.
    During the gate interval, subsequent TOT pulses may optionally be
    recorded. At the end of the gate period, a second timing pulse is
    generated with width proportional to the gated integral charge
    (after subtracting a pedestal). The pedestal may be as long as 300
    ns.  A single PE pulse of 25 pC will record a pedestal subtracted
    width of 2.5 ns, or 5 counts in the 1877 TDC system. Full scale will
    be approximately 200 PE = 1000 ns = 500 ns of TDC counts. The total
    deadtime for a full-scale pulse is basically the 200 ns gate-width +
    300 ns pedestal + 1000 ns of encoded Q = 1500 ns.