based on notes from Texas mtg:
P.Green, E. Kearns, Y.Lu, A.Sanzgiri, B.Webb
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This note contains the proposed QC specifications for WFD motherboard
testing, to be performed at TAMU following delivery from the board
assembler (Texas Instruments). This list is a starting point; the
tests require refinement of detail. We are also open to suggestions
from other WFD users.
1) With a DVM, measure the resistance between the -2V, +5V, -5.2V,
+6V, -6V and GND busses on the P3 connector. This will catch a
short between the supplies before the card is plugged in for the
first time.
2) RAM testing: write an assortment of patterns into 64K of channel
memory and read back. This catches shorts or disconnected pins in the
RAM section of the pcb. Test patterns: 0xAAAAAAAA, 0x55555555,
0xFFFFFFFF and 0x00000000. This also tests the read/write bit of the
control register.
3) RAM testing: write a unique number into each address and read back.
This will catch misconnections on the address lines.
Note: ETK has observed a glitch that occurs during the first RAM test
after power-on. It usually occurs in one of the wfd special addresses:
0xFFE0 or 0xFFF0 - 0xFFFC. It disappears during the 2nd test and never
reappears. ETK proposes: ignore this glitch.
4) With no input signal, operate WFD with zero suppression off and
discriminator set to 0xFF. Scan RAM and verify that time words decrement
by 4, discriminator bits are 0. This checks that ASIC is basically
functioning and that zero suppression can be turned off.
5) Put in a 100 ns wide negative pulse (-1V) with a 1.31 ms period. Put
zero suppression on and rollover on. Run WFD and verify that data
structure makes sense. ETK will send C program to give ideas. This
checks that zero suppression works and tests rollover function. This
program will also start readout from the stop-address and test the
stop-address readback function.
6) Run threshold setting program that sets 12 inputs to 12 unique
values. Measure with DVM on the daughtercard connector. This tests the
threshold DAC circuitry and control.
7) Full test A: put 100 kHz pulses into wfd with zero suppression on
and reconstruct graphically.
8) Full test B: run wfd overnight, periodically stopping and reading out.
9) (Optional?) Test VME reset bit. Arrange stop pulse to come a short
known interval after the start pulse. Zero suppression is off. Execute
VME reset function. Put a single shot of START followed by STOP into
WFD. Execute the last address function. VME reset puts the address
pointer at the final channel address (0xFFFC); a short interval of
operation should fill the last few addresses of the wfd. This function
is not planned for MACRO running.
10) (Optional?) Put a 0 to -2V triangle or sawtooth directly into the
FADC input (no daughtercard, signal may be plugged into appropriate
daughtercard connecter hole). This will test that all FADC codes are
present.
11) (Optional?) Measure current draw of each card (STOPPED and STARTED).
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